Lab 3: Reaction Timer and Traffic Light



The purpose of this lab was twofold. The initial task involved the creation of a Reaction Counter, a device capable of displaying human reaction speed to visual stimulus to tens of milliseconds. The second aspect of the project was to create a variable traffic light that could react to two inputs, a button or sensor pad on both the north / south and the east / west lights.

Design Process

The entire lab was completed in VHDL (This includes both the reaction timer and the traffic light). The only physical circuitry involved was the 7128 chip on the Altera board, and the corresponding buttons, wires, and LED's. We began both state machine designs by looking at a state diagram in order to analyze which internal (i.e. clock cycles and LFSR's) and external (i.e. Buttons) would prompt the chip to shift to the next state. Our two state diagrams used in the design process are shown below:


Figure 1: Traffic Light State Machine (Does not show Reset path back to NRER)


Figure 2: Reaction Timer VHDL (Does not show Reset path back to WAIT state)




Both our circuits were extremely successful in Quartus II 4.0 Simulation. With the traffic light we were able to demonstrate a working variable delay traffic light during the labratory session to both Professor Maxwell and Professor Morsehet. We were also able to show the traffic light and reaction timer working using a waveform analysis tool in Altera's Quartus program, as seen below.

Figure 3: Waveform for traffic light




Figure 4: Waveform for Reaction Timer

You can see the output to the 7 digit display changing with each "clock" cycle (called "ct", our clock running the display only incremented every 2500 clock cycles to bring the processor down to a frequency of one megahertz.) until the BUTTON_REACT is pressed, upon which the clock stops running and the state shifts back to the default (WAIT) state.


Unfortunately, even after commenting out portions of the code using binary search methods; rewriting aspects of it, and placing it in new project files, we - Jonathan with the assistance of Michael Stone and Tali Moreshet - were unable to get any response from the altera board (we also varied altera boards.) after going to the reset state. However, because we were able to show a working example of the Altera board through the traffic light of a state machine running, and could simulate the reaction timer to work within Quartus, professor Maxwell has allowed us to submit the simulation as proof of a hypothetically working version of the Reaction Timer. Unfortunately, we will not be able to compete against each other to see who reacts faster. However, it is the best estimate of the group that Marie would have the faster time as Jonathan has almost no experience with computer games and or video games, and reaction to various visual stimulus leading to a physical response (button pressing) will not be as ingrained as his more technologically savvy partner.


The main issues we encountered revolved around my fragmented ability to program, especially in VHDL. However, with the assistance of Tali, Bruce, Taylor and Kelly I was able to overcome this lack of formal training in coding, and through coaching was able to put my ideas into numbers and letters. I experienced no difficulties in developing either state machine. With Bruce's help I used various techniques in monitoring signals in waveform analysis, and was able to debug my circuit after continual failure to produce the counting output I was seeking in simulation. With the help of Tali and Michael, we were able to debug the circuit additionally to show that the code was working. Our major issue remained our inability to get a response from the Altera board despite having loaded Michael's previously functioning circuit, or our circuit - which functioned perfectly in simulation. We have not been able to identify the issue with the physical chip and or code that is limiting it's ability to give an output on the board itself.

What We Learned

This was a very valuable experience in learning more about the capabilities and shortcomings of VHDL. I learned about the difficulties of putting delays into circuits. I also didn't realize that a random number generator would be so difficult to create (conceptually, once spelled out, implementation in VHDL was a piece of cake.). We also learned how writing code independently and trying to put it together, or working off of each other's code when not written together without solid documentation is nearly impossible. I learned that naming variables sensible things can make reading code so much easier. Most of the lessons revolved around VHDL and communication skills when working as a team on a project.