Architecture and Instruction Set
The SSC machine has a simple RISC Harvard architecture. It has a small number of registers, a data memory, and a program memory. The registers will be explained with the instruction set, but a few notes here will help. The Accumulator is the central part of the Arithmetic Logic Unit. All data and code come into and go out of the computer through the Memory Buffer Register. The Program Counter auto-increments on every instruction fetch and points to the next instruction to be fetched. Other registers will be described as needed.
The instruction set consists of three groups of instructions: arithmetic, memory access, and program control.
Arithmetic instructions operate on the Accumulator and sometimes one other operand. Increment, Decrement, Left Logical Shift, Right Logical Shift, and Invert all operate on the Accumulator alone. And M(X) and Add M(X) operate on one value fetched from memory and the Accumulator. Swap operates on the Accumulator and MQ. These are included in the SSC instruction set; we this set with a few other instructions. Negation (NEG) does a two's complement negation of the Accumulator. Add MQ adds the Accumulator and the MQ, leaving the result in the Accumulator. Subtraction and Multiplication are done in hardware, and store results in the Accumulator and sometimes the MQ. These instructions give our CPU the ability to do a variety of simple operations on integers.
Memory access and I/O are performed with a variety of Load and Store instructions. The standard Load and Store instructions place a 5-bit address into the Memory Address Register, which is then used to select a memory location for a read or write. The instruction set also supports an immediate load, with the 8-bit value stored in the instruction itself, and an indirect load via an address stored in the MQ register.
The SSC instruction set supports several branching modes. In addition to a direct (branchless) jump, branches can be executed based on the sign bit of the Accumulator or either of the two bits in the Flags register (CarryOut and Overflow). Our implementation also allows for a Halt instruction, which halts the processor until it is reset to its initial state with a user override.
All of these virtual registers exist as unsigned integers in software. All but the MBR, which occupies a 16-bit word, and the flags, which are individual bits, occupy 1 byte in memory, although registers like the PC or the MAR do not use all of the memory space allocated to them. In the case of registers in spaces larger than their actual range, the least significant bits count. So, for example, the MBR is the lowest 10 bits of a 16-bit unsigned integer in memory.
In addition to simulating and displaying the registers, our program included I/O and memory, which are displayed on the fourth row of the LED matrix and on the LCD display, respectively. To give the user a better idea of what's actually happening, the computer displays not only the ROM and RAM contents pointed to by the MBR, but also their immediate neighbors, on the LCD.
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Alexandr Pshenichkin and Cortland Setlow
Swarthmore College