CS23 Lab 3
Building a Simple Computer
A simple CPU was designed and built in VHDL. It utilized a three-bus architecture, with five eight bit registers, and a twenty bit instruction. Numbers are represented in twos complement binary form. All data passes through the ALU on each cycle; the ALU is implemented as an asynchronous circuit within the CPU. Flags from the ALU, which indicate the sign of the previous output of the ALU, were mirrored in a register using the inout signal type in VHDL, so that these flags could be read from the CPU. Sixteen instructions were defined and implemented for the CPU, and instructions were stored in a ROM using the Altera lpm_rom macrofunction. To make writing software for the CPU easier, an assembly language was designed and an assembler was written in Java. In order to implement a twos compliment division algorithm, an instruction was added to compare the signs of two registers and set the flags accordingly, without using a temporary register. This obviated the need for adding registers, which would also have required adding bits to the instruction to address the new registers.
A description of what we did and our design process
Our answers to some questions about the lab
Our extensions to the lab
The problems we encounterd and how we solved them
If our programs worked and how we tested them to find out
What we learned and suggestions for the lab