LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY scoreboard IS
	PORT(
		rst, clk, cds:	IN		STD_LOGic;
		dswitches: 	IN		std_logic_vector(13 downto 0);
		lights : OUT	STD_LOGIC_VECTOR(3 downto 0));
END scoreboard;

ARCHITECTURE scoreboard_behavior OF scoreboard IS
	component program_memory
		port(memory: in	std_logic_vector(3 downto 0);
			 q: out	std_logic_vector(13 downto 0));
	end component;
	component accumulator
		port(clk, rst: in std_logic;
			 data1: in std_logic_vector(3 downto 0);
			 data2: in std_logic_vector(3 downto 0);
 			 cont: in std_logic_vector(2 downto 0);
			 aquaman: out std_logic_vector(3 downto 0);
			 counter3: out std_logic);
	end component;
	component light_register
		port(clk, rst: in std_logic;
			 data1: in std_logic_vector(7 downto 4);
			 aquaman: in std_logic_vector(3 downto 0);
			 light_control: in std_logic_vector(9 downto 8);
			 data2: out std_logic_vector(3 downto 0);
			 lights: out std_logic_vector(3 downto 0));
	end component;
	component instruction_register
		port(clk, rst, cds: in std_logic;
			 q, dswitches: in std_logic_vector(13 downto 0);
			 counter1: out std_logic_vector(3 downto 0);
			 data1: out std_logic_vector(7 downto 4);
			 light_control: out std_logic_vector(9 downto 8);
			 cont: out std_logic_vector(12 downto 10);
			 counter2: out std_logic);
	end component;
	component program_counter
		port(counter2: in std_logic;
			 counter3: in std_logic;
			 counter1: in std_logic_vector(3 downto 0);
			 memory: out std_logic_vector(3 downto 0));
	end component;
signal memory, data2, aquaman, counter1: std_logic_vector(3 downto 0);
signal cont: std_logic_vector(12 downto 10);
signal data1: std_logic_vector(7 downto 4);
signal counter2, counter3: std_logic;
signal light_control: std_logic_vector(9 downto 8);
signal q: std_logic_vector(13 downto 0);
	   
BEGIN
	pm: program_memory port map(memory,q);
	pc: program_counter port map(counter2, counter3, counter1, memory);
	lr: light_register port map(clk, rst, data1, aquaman, light_control, data2, lights);
	ac: accumulator port map(clk, rst, data1, data2, cont, aquaman, counter3);
	ir: instruction_register port map(clk, rst, cds, q, dswitches, counter1, 
									  data1, light_control, cont, counter2);
END scoreboard_behavior;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY lab1 IS
	PORT(
		rst, clk, cds:	IN		STD_LOGic;
		dswitches:		IN		std_logic_vecToR(13 downto 0);
		lights : OUT	STD_LOGIC_VECTOR(3 downto 0));
		
END lab1;

ARCHITECTURE lab1_behavior OF lab1 IS
	component scoreboard
		port(rst, clk, cds: in	std_logic;
			 dswitches:		in std_logic_vecTOr(13 downto 0);
			 lights: out	std_logic_vector(3 downto 0));
	end component;
	component clockdivider
		port(rst, clk: in std_logic;
			 clockbits: out std_logic_vector(7 downto 0));
	end component;
	signal clockbits: std_logic_vector(7 downto 0);	   
	
BEGIN
		cd: clockdivider port map(rst, clk, clockbits);
		sb: scoreboard port map(rst, clockbits(7), cds, dswitches, lights);
				
END lab1_behavior;



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